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80807hkim 20060405-s00011 no.a0137-1/22 ver.1.07 LC87F1364A overview the sanyo LC87F1364A is an 8-bit microcomputer that, ce ntered around a cpu running at a minimum bus cycle time of 166ns, integrates on a single chip a number of hardware features such as 64k-byte flash rom (onboard programmable), 1024-byte ram, an on-chip debugger, a sophisticated 16-bit timers/counters (may be divided into 8-bit timers), 16-bit timers (may be divided into 8-bit timers or 8-bit pwms), four 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, a high-speed clock counter, a synchronous sio interface (with automatic block transmit/ receive function), an asynchronous/synchronous sio inte rface, a uart interface (full duplex), a usb (low-speed) interface, two 12-bit pwm channels, an 8-bit 9-channel ad converter, and a 29-source 10-vector address interrupt feature. features ? flash rom ? block-erasable in 128-byte units ? 65536 8 bits ? minimum bus cycle time ? 166 ns (cf = 6mhz) note: the bus cycle time here refers to the rom read speed. ? minimum instruction cycle time (tcyc) ? 500 ns (cf = 6mhz) ordering number : ena0137 cmos ic from 64k byte, ram 1k byte on-chip 8-bit 1-chip microcontroller with low-speed usb * this product is licensed from silicon storage te chnology, inc. (usa), and manufactured and sold by sanyo semiconductor co., ltd. specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
LC87F1364A no.a0137-2/22 ? ports ? i/o ports ports whose i/o direction can be designated in 1 bit units 9 (p1n, p70) ports whose i/o direction can be designated in 4 bit units 8 (p0n) ? usb ports 2 (d+, d-) ? dedicated oscillator ports 2 (xt1, xt2) ? reset pins 1 ( res ) ? power pins 1 (v ss 1, v dd 1) ? timers ? timer 0: 16-bit timer/counter with a capture register. mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture registers) 2 channels mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture registers) + 8-bit counter (with an 8-bit capture register) mode 2: 16-bit timer with an 8-bit programma ble prescaler (with a 16-bit capture register) mode 3: 16-bit counter (with a 16-bit capture register) ? timer 1: 16-bit timer that supports pwm/toggle output capabilities) mode 0: 8-bit timer with an 8-b it prescaler (with toggle outputs) 2 channels mode 1: 8-bit pwm with an 8-bit prescaler 2 channels mode 2: 16-bit timer with an 8-bit prescaler (with toggle output) (the lower-order 8 bits can be used as a timer with toggle output.) mode 3: 16-bit timer with an 8-bit prescaler (with toggle output) (the lower-order 8 bits can be used as pwm.) ? base timer 1) the clock is selectable from the subclock (32.768khz crystal oscillation), system clock, and timer 0 prescaler output. 2) interrupts programmable in 5 different time schemes ? timer 4: 8-bit timer with a 6-bit prescaler ? timer 5: 8-bit timer with a 6-bit prescaler ? timer 6: 8-bit timer with a 6-bit prescaler ? timer 7: 8-bit timer with a 6-bit prescaler ? sio ? sio0: synchronous serial interface 1) lsb first/msb first mode selectable 2) built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3tcyc ) 3) automatic continuous data transmission (1 to 256 bits) ? sio1: 8-bit asynch ronous/synchronous serial interface mode 0: synchronous 8-bit serial i/o (2- or 3-wire configuration, 2 to 512 tcyc transfer clocks) mode 1: asynchronous serial i/o (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tcyc baudrates) mode 2: bus mode 1 (start bit, 8 data bits, 2 to 512 tcyc transfer clocks) mode 3: bus mode 2 (start detect, 8 data bits, stop detect) ? full duplex uart ? uart1 1) data length: 7/8/9 bits selectable 2) stop bits: 1 bit (2 bits in continuous transmission mode) 3) baud rate: 16/3 to 8192/3 tcyc ? ad converter: 8 bits 9 channels ? pwm: multifrequency 12-bit pwm 2 channels
LC87F1364A no.a0137-3/22 ? usb controller ? usb specification rev. 1.1 (low-speed) compatible ? supports a maximum of 2 user-defined endpoints. endpoint ep0 ep1 ep2 control enable enable - transfer type interrupt - enable enable max. payload 8 8 8 ? watchdog timer ? external rc watchdog timer ? interrupt and reset signals selectable ? interrupts ? 29 sources, 10 vector addresses 1) provides three levels (low (l), high (h), and highest (x )) of multiplex interrupt control. any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the smallest vector address takes precedence. no. vector address level interrupt source 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l/usb bus active 4 0001bh h or l int3/base timer 5 00023h h or l t0h 6 0002bh h or l t1l/t1h 7 00033h h or l sio0/usb bus re set/usb suspend/uart1 receive 8 0003bh h or l sio1/usberr/usbpov/usben p/usbnak/ usbstl/ uart1 transmit 9 00043h h or l adc/t6/t7 10 0004bh h or l port 0/pwm0/pwm1/t4/t5 ? priority levels x > h > l ? of interrupts of the same level, the one with the smallest vector address takes precedence. ? subroutine stack levels: 512 levels (the stack is allocated in ram.) ? high-speed multiplication/division instructions ? 16 bits 8 bits (5 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? 16 bits 8 bits (8 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? oscillation circuits ? rc oscillation circuit (internal): for system clock ? cf oscillation circuit: for system clock, usb interface ? crystal oscillation circuit: for system clock, time-of-day clock ? pll circuit (internal): for system clock, usb interface
LC87F1364A no.a0137-4/22 ? standby function ? halt mode: halts instruction execution while allowing the peripheral circuits to continue operation. 1) oscillation is not halted automatically. 2) canceled by a system reset or occurrence of an interrupt. ? hold mode: suspends instruction execution and the operation of the peripheral circuits. 1) the pll base clock generator, cf, rc and cr ystal oscillators automatically stop operation. 2) there are four ways of resetting the hold mode. (1) setting the reset pin to the lower level. (2) setting at least one of the int0, int1, and int2 pins to the specified level (3) having an interrupt source established at port 0 (4) having an bus active interrupt source established in the usb interface circuit ? x'tal hold mode: suspends instruction execution and the opera tion of the peripheral circu its except the base timer. 1) the pll base clock generator, cf and rc oscillator automatically stop operation. 2) the state of crystal oscillation established wh en the x'tal hold mode is entered is retained. 3) there are five ways of resetting the x'tal hold mode. (1) setting the reset pin to the low level (2) setting at least one of the int0, int1, and int2 pins to the specified level (3) having an interrupt source established at port 0 (4) having an interrupt source established in the base timer circuit (5) having an bus active interrupt source established in the usb interface circuit ? package form ? mfp24s(300mil): lead-free type ? development tools ? on-chip debugger: tcb87 type-a or tcb87 type-b + LC87F1364A ? flash rom programming boards package programming boards mfp24s(300mil) w87f5300m ? recommended eprom programmer maker model supported version device flash support group, inc. (single) af9708/af9709/af9709b (including product of ando electric co.,ltd) after 02.40 LC87F1364A sanyo skk(sanyo fws) application version: after 1.03 chip data version: after 2.01 lc87f1364
LC87F1364A no.a0137-5/22 package dimensions unit : mm (typ) 3112b pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 p05/an5/cko p06/an6/t6o p07/an7/t7o p70/int0/t0lcp/an8/dpup d+ d- res p17/filt v ss 1 xt1/cf1 xt2/cf2 v dd 1 p04/an4/dbgp2 p03/an3/dbgp1 p02/an2/dbgp0 p01/an1/urx1 p00/an0/utx1 p16/pwm1 p15/sck1/int3/t0in/pwm0 p14/si1/sb1/int2/t0in p13/so1/int1/t0hcp p12/sck0 p11/si0/sb0 p10/so0 mfp24s top view sanyo : mfp24s(300mil) 1 12 13 24 12.5 0.63 7.6 5.4 0.15 1.0 0.35 (0.75) 1.7max 0.1 (1.5)
LC87F1364A no.a0137-6/22 mfp name 1 p05/an5/cko 2 p06/an6/t6o 3 p07/an7/t7o 4 p70/int0/t0lcp/an8/dpup 5 d+ 6 d- 7 res 8 p17/filt 9 v ss 1 10 xt1/cf1 11 xt2/cf2 12 v dd 1 13 p10/so0 14 p11/si0/sb0 15 p12/sck0 16 p13/so1/int1/t0hcp 17 p14/si1/sb1/int2/t0in 18 p15/sck1/int3/t0in/pwm0 19 p16/pwm1 20 p00/an0/utx1 21 p01/an1/urx1 22 p02/an2/dbgp0 23 p03/an3/dbgp1 24 p04/an4/dbgp2
LC87F1364A no.a0137-7/22 system block diagram interrupt control flash-rom standby control clock generator rc cf/x?tal pll ir pla pc timer 7 bus interface port 0 port 1 port 7 acc b register c register alu psw rar ram stack pointer watchdog timer timer 4 pwm0 int0 to 3 noise rejection filter sio0 uart1 adc sio1 timer 0 timer 1 timer 5 timer 6 base timer pwm1 usb interface on-chip-debugger
LC87F1364A no.a0137-8/22 pin description pin name i/o description option v ss 1 - - power supply pin no v dd 1 - + power supply pin no port 0 p00 to p07 i/o ? 8-bit i/o port ? i/o specifiable in 4 bit units ? pull-up resistors can be turned on and off in 4 bit units. ? hold reset input ? port 0 interrupt input ? pin functions p00: an0 (adc input)/uart1 transmit p01: an1 (adc input)/uart1 receive p02: an2 (adc input)/for on-chip-debugger p03: an3 (adc input)/for on-chip-debugger p04: an4 (adc input)/for on-chip-debugger p05: an5 (adc input)/system clock output p06: an6 (adc input)/timer 6 toggle outputs p07: an7 (adc input)/timer 7 toggle outputs yes port 1 p10 to p17 i/o ? 8-bit i/o port ? i/o specifiable in 1 bit units ? pull-up resistors can be turned on and off in 1 bit units. ? pin functions p10: sio0 data output p11: sio0 data input/bus i/o p12: sio0 clock i/o p13: sio1 data output/i nt1 input/hold reset input/timer oh capture input p14: sio1 data input/bus i/o/int2 input/ hold reset input/timer 0 event input/timer ol capture input p15: sio1 clock i/o/int3 inpu t (with noise filter)/timer 0 event input/timer oh capture input /pwm 0 output p16: timer 1 pwml output/pwm 1 output p17: timer 1 pwmh output/beeper out put/internal pll filter pin interrupt acknowledge type rising falling rising & falling h level l level int1 enable enable disable enable enable int2 enable enable enable disable disable int3 enable enable enable disable disable yes port 7 ? 1-bit i/o port ? i/o specifiable in 1 bit units ? pull-up resistors can be turned on and off in 1 bit units. ? shared pins p70: int0 input/hold reset input/timer 0l capt ure input/watchdog timer output/an8 (adc input) / d- 1.5k ? pull-up resistor connect pin interrupt acknowledge type rising falling rising & falling h level l level int0 enable enable disable enable enable p70 i/o no res i reset pin no xt1 i ceramic oscillator input pin/32.768khz crystal oscillator input pin no xt2 i/o ceramic oscillator input pin/32.76 8khz crystal oscillator output pin no d- i/o usb data i/o pin d- no d+ i/o usb data i/o pin d+ no
LC87F1364A no.a0137-9/22 port output types the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port name option selected in units of option type output type pull-up resistor 1 cmos programmable (note 1) p00 to p07 1 bit 2 nch-open drain no 1 cmos programmable p10 to p17 1 bit 2 nch-open drain programmable p70 - no nch-open drain programmable xt1 - no input only no xt2 - no 32.768khz crystal oscillator output no note 1: programmable pull-up resistors for port 0 are controlled in 4 bit units (p00 to 03, p04 to 07). usb reference power option when a voltage 4.5v to 5.5v is supplied to v dd 1 and the internal usb reference vo ltage circuit is activated, the h output level of the usb port is 3.0v to 3.6v (the h output level of the ports except the usb port is the v dd 1 voltage level, however). the active/inactive state of the referenc e voltage circuit can be determined by option settings. according to the voltage to be supplied to v dd 1, make option settings as shown below. v dd 1 voltage (v) 4.5 to 5.5 3.0 to 3.6 usb regulator use use use nonuse usb regulator in hold m ode use nonuse nonuse nonuse option setting usb regulator in halt mode use nonuse use nonuse normal state active active active inactive hold mode active inactive inactive inactive reference voltage circuit state halt mode active inactive active inactive (1) (2) (3) (4) ? when the usb reference voltage circuit is made inactiv e, the h output level of the usb port becomes the v dd 1 voltage level. ? use the setting (2) or (3) to make the reference voltage circuit inactive in hold or halt mode. ? when the reference voltage circuit is activated , the current drain increases by approximately 100 a compared with when the reference voltage circuit is inactive.
LC87F1364A no.a0137-10/22 absolute maximum ratings at ta = 25c, v ss 1 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit maximum supply voltage v dd max v dd 1 v dd 1 -0.3 +6.5 input voltage v i (1) xt1, xt2 -0.3 v dd +0.3 input/output voltage v io (1) ports 0, 1, 7 -0.3 v dd +0.3 v ioph(1) ports 0, 1 ? when cmos output type is selected ? per 1 applicable pin -10 peak output current ioph(2) pwm0, pwm1 per 1 applicable pin -20 iomh(1) ports 0, 1 ? when cmos output type is selected ? per 1 applicable pin -7.5 average output current (note 2) iomh(2) pwm0, pwm1 per 1 applicable pin -15 high level output current total output current ioah(1) ports 0, 1 pwm0, pwm1 d+, d- total of all applicable pins -50 iopl(1) p00 to p05 ports 1, p70 pwm0, pwm1 per 1 applicable pin 20 peak output current iopl(2) p06, 07 per 1 applicable pin 30 ioml(1) p00 to p05 ports 1, p70 pwm0, pwm1 per 1 applicable pin 15 average output current (note 2) ioml(2) p06, 07 per 1 applicable pin 20 low level output current total output current ioal(1) ports 0, 1, p70 pwm0, pwm1 d+, d- total of all applicable pins 75 ma allowable power dissipation pd max mfp24s ta=-20 to +70 c mw operating ambient temperature topr -20 +70 storage ambient temperature tstg -55 +125 c note 2: the mean output current is a mean value measured over 100ms.
LC87F1364A no.a0137-11/22 allowable operating conditions at ta = -20c to +70c, v ss 1 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit v dd (1) 0.490s tcyc 200s except for onboard programming (note 3) 2.5 5.5 operating supply voltage v dd (2) v dd 1 0.490s tcyc 200s internal pll oscillation 4.5 5.5 memory sustaining supply voltage vhd v dd 1 ram and register contents sustained in hold mode. 2.0 5.5 v ih (1) port 1 p70 port input /interrupt side 2.5 to 5.5 0.3v dd +0.7 v dd v ih (2) port 70 watchdog timer side 2.5 to 5.5 0.9v dd v dd high level input voltage v ih (3) xt1, xt2, res 2.5 to 5.5 0.75v dd v dd 4.0 to 5.5 v ss 0.1v dd +0.4 v il (1) port 1 p70 port input /interrupt side 2.5 to 4.0 v ss 0.2v dd 4.0 to 5.5 v ss 0.15v dd +0.4 v il (2) port 0 2.5 to 4.0 v ss 0.2v dd v il (3) port 70 watchdog timer side 2.5 to 5.5 v ss 0.8v dd -1.0 low level input voltage v il (4) xt1, xt2, res 2.5 to 5.5 v ss 0.25v dd v instruction cycle time (note 4) tcyc 2.5 to 5.5 0.490 200 s ? xt2 pin open ? system clock frequency division ratio=1/1 ? external system clock duty =50 5% 2.5 to 5.5 0.1 6 external system clock frequency fexcf(1) xt1 ? xt2 pin open ? system clock frequency division ratio=1/2 2.5 to 5.5 0.1 12 mhz fmcf xt1, xt2 6mhz ceramic oscillation see fig. 1. 2.5 to 5.5 6 fmrc internal rc oscillation 2.5 to 5.5 0.3 1.0 2.0 mhz oscillation frequency range (note 5) fsx?tal xt1, xt2 32.768khz crystal oscillation see fig. 2. 2.5 to 5.5 32.768 khz note 3: v dd must be held greater than or equal to 3.0v in the flash rom onboard programming mode. note 4: relationship between tcyc and oscillation frequency is 3/fmcf at a division ratio of 1/1 and 6/fmcf at a division ratio of 1/2. note 5: see tables 1 and 2 for the oscillation constants.
LC87F1364A no.a0137-12/22 electrical characteristics at ta = -20c to +70c, v ss 1 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit i ih (1) ports 0, 1 port 70 res output disabled pull-up resistor off v in =v dd (including output tr's off leakage current) 2.5 to 5.5 1 high level input current i ih (2) xt1, xt2 v in =v dd 2.5 to 5.5 1 i il (1) ports 0, 1 port 70 res output disabled pull-up resistor off vin=v ss (including output tr's off leakage current) 2.5 to 5.5 -1 low level input current i il (2) xt1, xt2 v in =v ss 2.5 to 5.5 -1 a v oh (1) i oh =-1ma 4.5 to 5.5 v dd -1 v oh (2) i oh =-0.4ma 3.0 to 5.5 v dd -0.4 v oh (3) ports 0, 1 i oh =-0.2ma 2.5 to 5.5 v dd -0.4 v oh (4) i oh =-10ma 4.5 to 5.5 v dd -1.5 v oh (5) i oh =-1.6ma 3.0 to 5.5 v dd -0.4 high level output voltage v oh (6) pwm0, pwm1 p05 (ck0 when using system clock output function) i oh =-1ma 2.5 to 5.5 v dd -0.4 v ol (1) i ol =10ma 4.5 to 5.5 1.5 v ol (2) i ol =1.6ma 3.0 to 5.5 0.4 v ol (3) ports 0, 1 port 70 pwm0, pwm1 i ol =1ma 2.5 to 5.5 0.4 v ol (4) i ol =30ma 4.5 to 5.5 1.5 v ol (5) i ol =5ma 3.0 to 5.5 0.4 low level output voltage v ol (6) p06, p07 i ol =2.5ma 2.5 to 5.5 0.4 v rpu(1) 4.5 to 5.5 15 35 80 pull-up resistance rpu(2) ports 0, 1 port 70 v oh =0.9v dd 2.5 to 5.5 18 50 150 k ? hysteresis voltage vhys res port 1 port 70 2.5 to 5.5 0.1v dd v pin capacitance cp all pins for pins other than that under test: v in =v ss f=1mhz ta=25 c 2.5 to 5.5 10 pf
LC87F1364A no.a0137-13/22 serial i/o characteristics at ta = -20c to +70c, v ss 1 = 0v 1. sio0 serial i/o characteristics (note 4-1-1) specification parameter symbol pin /remarks conditions v dd [v] min typ max unit frequency tsck(1) 2 low level pulse width tsckl(1) 1 tsckh(1) see fig. 6. 1 tsckha(1a) ? continuous data transmission/reception mode ? usb is not in use simultaneous. ? see fig. 6. ? (note 4-1-2) 4 input clock high level pulse width tsckha(1b) sck0(p12) ? continuous data transmission /reception mode ? usb is in use simultaneous. ? see fig.6. ? (note 4-1-2) 2.7 to 5.5 7 frequency tsck(2) 4/3 tcyc low level pulse width tsckl(2) 1/2 tsckh(2) ? cmos output selected ? see fig.6. 1/2 tsck tsckha(2a) ? continuous data transmission /reception mode ? usb is not in use simultaneous. ? cmos output selected ? see fig.6. tsckh(2) +2tcyc tsckh(2) +(10/3) tcyc serial clock output clock high level pulse width tsckha(2b) sck0(p12) ? continuous data transmission /reception mode ? usb is in use simultaneous. ? cmos output selected ? see fig.6. 2.7 to 5.5 tsckh(2) +2tcyc tsckh(2) +(19/3) tcyc tcyc data setup time tsdi(1) 2.7 to 5.5 0.03 serial input data hold time thdi(1) sb0(p11), si0(p11) ? must be specified with respect to rising edge of sioclk. ? see fig.6. 2.7 to 5.5 0.03 tdd0(1) ? continuous data transmission /reception mode ? (note 4-1-3) 2.7 to 5.5 (1/3)tcyc +0.05 input clock tdd0(2) ? synchronous 8-bit mode ? (note 4-1-3) 2.7 to 5.5 1tcyc +0.05 serial output output clock output delay time tdd0(3) so0(p10), sb0(p11) (note 4-1-3) 2.7 to 5.5 (1/3)tcyc +0.05 s note 4-1-1: these specifications are theoretical values. add margin depending on its use. note 4-1-2: to use serial-clock-input in continuous trans/rec mode, a time from si0run being set when serial clock is "h" to the first negative edge of the serial clock must be longer than tsckha. note 4-1-3: must be specified with respect to falling edge of sioclk. must be specified as the time to the beginning of output state change in open drain output mode. see fig.6.
LC87F1364A no.a0137-14/22 2. sio1 serial i/o characteristics (note 4-2-1) specification parameter symbol pin /remarks condiptions v dd [v] min typ max unit frequency tsck(3) 2 low level pulse width tsckl(3) 1 input clock high level pulse width tsckh(3) sck1(p15) see fig.6. 2.7 to 5.5 1 frequency tsck(4) 2 tcyc low level pulse width tsckl(4) 1/2 serial clock output clock high level pulse width tsckh(4) sck1(p15) ? cmos output selected ? see fig.6. 2.7 to 5.5 1/2 tsck data setup time tsdi(2) 2.7 to 5.5 0.03 serial input data hold time thdi(2) sb1(p14), si1(p14) ? must be specified with respect to rising edge of sioclk. ? see fig.6. 2.7 to 5.5 0.03 serial output output delay time tdd0(4) so1(p13), sb1(p14) ? must be specified with respect to falling edge of sioclk. ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig.6. 2.7 to 5.5 (1/3)tcyc +0.05 s note 4-2-1: these specifications are theoretical values. add margin depending on its use.
LC87F1364A no.a0137-15/22 pulse input conditions at ta = -20c to +70c, v ss 1 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit tp1h(1) tp1l(1) int0(p70), int1(p13), int2(p14), ? interrupt source flag can be set. ? event inputs for timer 0 or 1 are enabled. 2.5 to 5.5 1 tpih(2) tpil(2) int3(p15) when noise filter time constant is 1/1 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.5 to 5.5 2 tpih(3) tpil(3) int3(p15) when noise filter time constant is 1/32 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.5 to 5.5 64 tpih(4) tpil(4) int3(p15) when noise filter time constant is 1/128 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.5 to 5.5 256 tcyc high/low level pulse width tpil(5) res resetting is enabled. 2.5 to 5.5 200 s ad converter characteristics at ta = -20c to +70c, v ss 1 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 3.0 to 5.5 8 bit absolute accuracy et (note 6) 3.0 to 5.5 1.5 lsb 4.5 to 5.5 15.68 (tcyc= 0.49 s) 97.92 (tcyc= 3.06 s) ad conversion time = 32 tcyc (when adcr2=0) (note 7) 3.0 to 5.5 31.36 (tcyc= 0.98 s) 97.92 (tcyc= 3.06 s) 4.5 to 5.5 31.36 (tcyc= 0. 49 s) 97.92 (tcyc= 1.53 s) conversion time tcad ad conversion time = 64 tcyc (when adcr2=1) (note 7) 3.0 to 5.5 31.36 (tcyc= 0. 49 s) 97.92 (tcyc= 1.53 s) s analog input voltage range vain 3.0 to 5.5 v ss v dd v iainh vain=v dd 3.0 to 5.5 1 analog port input current iainl an0(p00) to an7(p07), an8(p70) vain=v ss 3.0 to 5.5 -1 a note 6: the quantization error ( 1/2lsb) is excluded from the absolute accuracy value. note 7: the conversion time refers to the interval from the ti me the instruction for starting the converter is issued till the time the complete digital value corresponding to the analog input value is loaded in the required register.
LC87F1364A no.a0137-16/22 consumption current characteristics at ta = -20c to +70c, v ss 1 = 0v specification parameter symbol pin /remarks conditions v dd [v] min typ max unit iddop(1) 4.5 to 5.5 5.3 13 iddop(2) ? fmcf=6mhz ceramic oscillation mode ? system clock set to 6mhz side ? internal rc oscillation stopped ? 1/1 frequency division ration 2.5 to 4.5 3.5 9.6 iddop(3) ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to pll clock side ? internal rc oscillation stopped ? 1/1 frequency division ration 4.5 to 5.5 6.7 17 iddop(4) 4.5 to 5.5 0.67 3.1 iddop(5) ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to internal rc oscillation ? internal pll oscillation stopped ? 1/2 frequency division ration 2.5 to 4.5 0.43 2.3 ma iddop(6) 4.5 to 5.5 120 380 normal mode consumption current (note 8) iddop(7) ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 32.768khz side ? internal rc oscillation stopped ? internal pll oscillation stopped ? 1/2 frequency division ration 2.5 to 4.5 79 290 a iddhalt(1) 4.5 to 5.5 2.0 5.4 iddhalt(2) ? halt mode ? fmcf=6mhz ceramic scillation mode ? system clock set to 6mhz side ? internal rc oscillation stopped ? 1/1 frequency division ration 2.5 to 4.5 1.2 3.6 iddhalt(3) ? halt mode ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to pll clock side ? internal rc oscillation stopped ? 1/1 frequency division ration 4.5 to 5.5 3.6 9.6 iddhalt(4) 4.5 to 5.5 0.33 1.6 iddhalt(5) ? halt mode ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to internal rc oscillation ? internal pll oscillation stopped ? 1/2 frequency division ration 2.5 to 4.5 0.19 1.1 ma iddhalt(6) 4.5 to 5.5 30 130 halt mode consumption current (note 8) iddhalt(7) ? halt mode ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 32.768khz side ? internal rc oscillation stopped ? internal pll oscillation stopped ? 1/2 frequency division ration 2.5 to 4.5 12 73 iddhold(1) 4.5 to 5.5 0.04 13 hold mode consumption current iddhold(2) hold mode ? xt1=v dd or open (external clock mode) 2.5 to 4.5 0.02 9.8 iddhold(3) 4.5 to 5.5 27 120 timer hold mode consumption current iddhold(4) v dd 1 timer hold mode ? fsx?tal=32.768khz crystal oscillation mode 2.5 to 4.5 9.6 66 a note 8: the consumption current value incl udes none of the currents that flow into the output tr and internal pull-up resistors.
LC87F1364A no.a0137-17/22 usb characteristics and timing at ta = -20c to +70c, v ss 1 = 0v specification parameter symbol conditions min typ max unit high level output v oh(usb) ? 15k ? 5% to gnd 2.8 3.6 v low level output v ol ? 1.5k ? 5% to 3.6v 0.3 v output signal crossover voltage v crs 1.3 2.0 v differential input sensitivity v di ? ? (d+)-(d-) ? 0.2 v differential input common mode range v cm 0.8 2.5 v high level input v ih(usb) 2.0 v low level input v il(usb) 0.8 v usb data rise time t r 75 300 ns usb data fall time t f 75 300 ns rise/fall time t rfm ? t r /t f 80 125 % f-rom write characteristics at ta = +10c to +55c, v ss 1 = 0v specification parameter symbol pin conditions v dd [v] min typ max unit onboard programming current iddfw(1) v dd 1 ? 128-byte programming ? erasing current included 3.0 to 5.5 25 40 ma programming time tfw(1) ? 128-byte programming ? erasing current included ? time for setting up 128-byte data excluded. 3.0 to 5.5 22.5 45 ms
LC87F1364A no.a0137-18/22 characteristics of a sample exte rnal clock oscillation circuit given below are the characteristics of a sample external clock oscillation circuit that are measured using a sanyo- designated oscillation characteristics evaluation board and exte rnal components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 1 characteristics of a sample external cl ock oscillator circuit with a crystal oscillator circuit constant oscillation stabilization time nominal frequency vendor name oscillator name c1 [pf] c2 [pf] rf1 [ ? ] rd1 [ ? ] operating voltage range [v] typ [s] max [s] remarks 32.768khz epson toyocom mc-306 22 22 open 820k 2.5 to 5.5 1.3 3 applicable cl value=12.5pf the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is ex ecuted and to the time interval that is required for the oscillation to get stabilized after the hold mode is reset (see figure 4). note: the components that are in volved in oscillation should be placed as close to the ic an d to one another as possible because they are vulnerable to the influences of the circuit pattern. figure 1 crystal oscillation circuit table 2 characteristics of a sample external clock oscillator circuit with a cf oscillator circuit constant oscillation stabilization time nominal frequency vendor name oscillator name c3 [pf] c4 [pf] rf2 [ ? ] rd2 [ ? ] operating voltage range [v] typ [ms] max [ms] remarks 6mhz murata cstcr6m00g15***-r 0 (39) (39) open 1k 2.5 to 5.5 0.1 0.5 built in c3, c4 the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after v dd goes above the operating voltage lower limit (see figure 4). figure 2 cf oscillation circuit rf1 rd1 xt1 xt2 c2 x?tal c1 rd2 xt1 xt2 c4 cf c3 rf2
LC87F1364A no.a0137-19/22 figure 3 ac timing measurement point reset time and oscillation stabilization time hold reset signal and oscillation stabilization time figure 4 oscillation stabilization times 0.5v dd internal rc oscillation cf oscillation (xt1, xt2) crystal oscillation (xt1, xt2) state hold reset signal hold reset signal absen hold reset signal valid tmscf tmsx?tal hold halt power supply res internal rc oscillation cf oscillation (xt1, xt2) crystal oscillation (xt1, xt2) state reset time tmscf tmsx?tal unpredictable reset instruction execut v dd operating v dd lower limit gnd
LC87F1364A no.a0137-20/22 figure 5 filter circuit for the internal pll circuit figure 6 reset circuit when using the internal pll circuit to generate the 6mhz clock for usb or system clock, it is necessary to connect a filter circuit such as that shown to the left to the p17/filt pin.. 0 ? 2.2 f p17/filt + - c res v dd r res res note: determine the value of c res and r res so that the reset signal is present for a period of 200s after the supply voltage goes beyond the lower limit of the ic's operating voltage.
LC87F1364A no.a0137-21/22 figure 7 serial input/output waveforms figure 8 pulse input timing signal waveform figure 9 usb data signal timing and voltage level tpil tpih data ram transfer period (sio0 only) data ram transfer period (sio0 only) di0 di7 di2 di3 di4 di5 di6 di8 do0 do7 do2 do3 do4 do5 do6 do8 di1 do1 sioclk: datain: dataout: dataout: datain: sioclk: dataout: datain: sioclk: tsck tsckl tsckh thdi tsdi tddo tsckla tsckha thdi tsdi tddo t r t r d+ d- 10% 10% 90% 90% v oh v crs v ol
LC87F1364A no.a0137-22/22 ps this catalog provides information as of july, 2 006. specifications and info rmation herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probabi lity. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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